View V53C318165A50_5224893.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mosel vitelic 1 v53c318165a 3.3 volt 1m x 16 edo page mode cmos dynamic ram v53c318165a rev. 1.0 january 1998 high performance 50 60 70 max. ras access time, (t rac ) 50 ns 60 ns 70 ns max. column address access time, (t caa ) 25 ns 30 ns 35 ns min. extended data out page mode cycle time, (t pc ) 20 ns 25 ns 30 ns min. read/write cycle time, (t rc ) 84 ns 104 ns 124 ns features n 1m x 16-bit organization n edo page mode for a sustained data rate of 50 mhz n ras access time: 50, 60, 70 ns n dual cas inputs n low power dissipation n read-modify-write, ras -only refresh, cas -before-ras refresh, hidden refresh, and self refresh. n refresh interval: 1024 cycles/16 ms n available in 42-pin 400 mil soj and 50/44-pin 400 mil tsop-ii n single +3.3 v 0.3 v power supply n ttl interface description the v53c318165a is a 1048576 x 16 bit high- performance cmos dynamic random access mem- ory. the v53c318165a offers page mode opera- tion with extended data output. the v53c318165a has an symmetric address, 10-bit row and 10-bit column. all inputs are ttl compatible. edo page mode operation allows random access up to 1024 x 16 bits, within a page, with cycle times as short as 20ns. these features make the v53c318165a ideally suited for a wide variety of high performance com- puter systems and peripheral applications. device usage chart operating temperature range package outline access time (ns) power temperature mark k t 50 60 70 std. 0 c to 70 c blank
2 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a 42-pin plastic soj pin configuration top view 50/44-pin plastic tsop-ii pin configuration top view v cc i/o 1 i/o 2 i/o 3 i/o 4 v cc i/o 5 i/o 6 i/o 7 i/o 8 nc nc we ras nc nc a 0 a 1 a 2 a 3 v cc v ss i/o 16 i/o 15 i/o 14 i/o 13 v ss i/o 12 i/o 11 i/o 10 i/o 9 nc lcas ucas oe a 9 a 8 a 7 a 6 a 5 a 4 v ss 5 6 7 8 9 10 11 12 1 2 3 4 40 39 38 37 36 35 34 33 32 31 30 29 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 311816500-02 42 21 41 v cc i/o 1 i/o 2 i/o 3 i/o 4 v cc i/o 5 i/o 6 i/o 7 i/o 8 nc nc nc we ras nc nc a 0 a 1 a 2 a 3 v cc v ss i/o 16 i/o 15 i/o 14 i/o 13 v ss i/o 12 i/o 11 i/o 10 i/o 9 nc nc lcas ucas oe a 9 a 8 a 7 a 6 a 5 a 4 v ss 5 6 7 8 9 10 11 1 2 3 4 48 47 46 45 44 43 42 41 40 15 16 17 18 19 20 36 35 34 33 32 31 30 29 28 27 26 311816500-03 50 21 22 23 24 25 49 description pkg. pin count soj k 42 tsop-ii t 50 pin names a 0 ? 9 row, column address inputs ras row address strobe ucas column address strobe/upper byte control lcas column address strobe/lower byte control we write enable oe output enable i/o 1 ?/o 16 data input, output v cc +3.3v supply v ss 0v supply nc no connect
3 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a block diagram a 0 a 1 a 8 a 9 sense amplifiers refresh counter v cc v ss 12 i/o 1 address buffers and predecoders row decoders memory array 1024 x 1024 x 16 column decoders data i/o bus y 0 ? 9 1024 x 16 311816500-04 1024 x 0 ?x 9 i/o buffer i/o 2 i/o 3 i/o 4 oe clock generator we clock generator cas clock generator ras clock generator oe we lcas ras i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 ucas 1024 x 16 absolute maximum ratings* operating temperature range .................. 0 to 70 c storage temperature range ............... -55 to 150 c soldering temperature .................................. 260 c soldering time ................................................... 10 s input/output voltage .... -0.5 to min (v cc +0.5, 4.6) v power supply voltage ........................ -0.5v to 4.6 v power dissipation .......................................... 0.5 w data out current (short circuit) ...................... 50 ma * note: operation above absolute maximum ratings can adversely affect device reliability. capacitance* t a = 25 c, v cc = 3.3 v 0.3 v, v ss = 0 v, f = 1 mhz * note: capacitance is sampled and not 100% tested. symbol parameter min. max. unit c in1 address input 5 pf c in2 ras , ucas , lcas , we , oe 7 pf c out data input/output 7 pf
4 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc = 3.3 v 0.3 v, v ss = 0 v, t t = 2ns, unless otherwise specified. symbol parameter access time v53c318165a unit test conditions notes min. typ. max. i li input leakage current (any input pin) ?0 10 m a v ss v in v cc + 0.3v 1 i lo output leakage current (for high-z state) ?0 10 m a v ss v out v cc + 0.3v ras , cas at v ih 1 i cc1 v cc supply current, operating 50 200 ma t rc = t rc (min.) 2, 3, 4 60 180 70 160 i cc2 v cc supply current, ttl standby 2 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 50 200 ma t rc = t rc (min.) 2, 4 60 180 70 160 i cc4 v cc supply current, edo page mode operation 50 90 ma minimum cycle 2, 3, 4 60 75 70 60 i cc5 v cc supply current, cmos standby 1.0 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v 1 i cc6 average self refresh current cbr cycle with t ras > t rass min., (l-version only) cas held low, we = v cc ?0.2v, address and d in = v cc ?0.2v or 0.2v 1.0 ma i cc7 v cc supply current, during cas -before- ras refresh 50 200 ma t rc = t rc (min) 2, 4 60 180 70 160 v il input low voltage ?.5 0.8 v 1 v ih input high voltage 2 v cc +0.5 v 1 v ol output low voltage 0.4 v i ol = 2 ma 1 v oh output high voltage 2.4 v i oh = ? ma 1
5 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a ac characteristics t a = 0 c to 70 c, v cc = 3.3 v 0.3 v, v ss = 0v, t t = 2ns unless otherwise noted # jedec symbol symbol parameter 50 60 70 unit notes min. max. min. max. min. max. 1 t rl1rh1 t ras ras pulse width 50 10k 60 10k 70 10k ns 2 t rl2rl2 t rc read or write cycle time 84 104 124 ns 3 t rh2rl2 t rp ras precharge time 30 40 50 ns 4 t rl1ch1 t csh cas hold time 40 50 60 ns 5 t cl1ch1 t cas cas pulse width 8 10k 10 10k 12 10k ns 6 t rl1cl1 t rcd ras to cas delay 12 37 14 45 14 53 ns 7 t wh2cl2 t rcs read command setup time 0 0 0 ns 8 t avrl2 t asr row address setup time 0 0 0 ns 9 t rl1ax t rah row address hold time 8 10 10 ns 10 t avcl2 t asc column address setup time 0 0 0 ns 11 t cl1ax t cah column address hold time 8 10 12 ns 12 t cl1rh1(r) t rsh ras hold time 13 15 17 ns 13 t ch2rl2 t crp cas to ras precharge time 5 5 5 ns 14 t ch2wx t rch read command hold time referenced to cas 0 0 0 ns 9 15 t rh2wx t rrh read command hold time referenced to ras 0 0 0 ns 9 16 t cl1 t coh output hold after cas low 5 5 5 ns 17 t gl1qv t oac access time from oe 13 15 17 ns 18 t cl1qv t cac access time from cas 13 15 17 ns 7, 12 19 t rl1qv t rac access time from ras 50 60 70 ns 7, 12 20 t avqv t caa access time from column address 25 30 35 ns 7, 13 21 t cl1qx t clz cas to low-z output 0 0 0 ns 7 22 t ch2qx t off output buffer turnoff delay 0 13 0 15 0 17 ns 23 t cl1qz t dzc data to cas low delay 0 0 0 ns 15 24 t rl1av t rad ras to column address delay time 10 25 12 30 12 35 ns 25 t gl2qz t oez output buffer turnoff delay from oe 0 13 0 15 0 17 ns 8 26 t wl1ch1 t cwl write command to cas lead time 13 15 17 ns 27 t wl1cl2 t wcs write command setup time 0 0 0 ns 11 28 t cl1wh1 t wch write command hold time 8 10 10 ns 29 t wl1wh1 t wp write pulse width 8 10 10 ns 30 t gl1qz t deo data to oe delay 0 0 0 ns 15 31 t wl1rh1 t rwl write command to ras lead time 13 15 17 ns 32 t dvwl2 t ds data in setup time 0 0 0 ns 10
6 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a 33 t wl1dx t dh data in hold time 8 10 12 ns 10 34 t wl1gl2 t woh write to oe hold time 10 13 15 ns 10 35 t ch2rh2 t prwc edo page mode read-write cycle time 58 68 77 ns 36 t rl2rl2 (rmw) t rwc read-modify-write cycle time 113 138 162 ns 38 t cl1wl2 t cwd cas to we delay 27 32 36 ns 10 39 t rl1wl2 t rwd ras to we delay in read-modify-write cycle 64 77 89 ns 10 40 t avwl2 t awd column address to we delay 39 47 54 ns 10 41 t cl2cl2 t pc edo page mode read or write cycle time 20 25 30 ns 42 t ch2cl2 t cp cas precharge time 8 10 10 ns 43 t avrh1 t car column address to ras setup time 25 30 35 ns 44 t ch2qv t cap access time from column precharge 27 32 37 ns 6 46 t cl1rl2 t csr cas setup time cas -before- ras refresh 10 10 10 ns 47 t rh2cl2 t rpc ras to cas precharge time 5 5 5 ns 48 t rl1ch1 t chr cas hold time cas -before- ras refresh 10 10 10 ns 50 t rh2cl2 t rasp ras pulse width (edo mode) 50 200k 60 200k 70 200k ns 51 t rh2cl2 t rhcp cas precharge time to ras delay 27 32 37 ns 52 t rh2cl2 t cpwd cas precharge time to we 41 49 56 ns 53 t rh2cl2 t cpt cas precharge time (cbr counter test) 35 40 40 ns 54 t rh2cl2 t wrp write to ras precharge time (crb cycle) 10 10 10 ns 55 t rh2cl2 t wrh write hold time reference to ras (crb cycle) 10 10 10 ns 56 t rh2cl2 t cdd cas high to data delay 10 13 15 ns 16 57 t rh2cl2 t odd oe high to data delay 10 13 15 ns 16 58 t t t t transition time (rise and fall) 1 50 1 50 1 50 ns 59 t ref refresh interval (1024 cycles) 16 16 16 ms self refresh ac characteristics 60 t rass ras pulse width during self refresh 100k 100k 100k ns 17 61 t rps ras precharge time during self refresh 95 110 130 ns 17 62 t chs cas hold time width during self rerfresh 50 50 50 ns 17 # jedec symbol symbol parameter 50 60 70 unit notes min. max. min. max. min. max. ac characteristics (cont?)
7 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a notes: 1. all voltage are referenced to v ss . 2. i cc1 , i cc3 , i cc4 , and i cc7 depend on cycle rate. 3. i cc1 and i cc4 depend on output loading. specified values are measured with the output open. 4. address can be changed once or less while ras = v il . in the case of i cc4 it can be changed once or less during an edo cycle (t hpc ). 5. an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas -before- ras initialization cycles instead of 8 ras cycles are required. 6. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also mea- sured between v ih and v il . 7. measured with a load equivalent to 2 ttl gates and 50 pf (v ol = 0.8v and v oh = 2.0v). 8. t off (max.) and t oez (max.) define the time at which the outputs acheive the open-circuit condition and are not ref- erenced to output voltage levels. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles. 11. t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.), the cycle is an early write cycle and the i/o pin will remain open- circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.), t cwd > t cwd (min.), t awd > t awd (min.), and t cpwd > t cpwd (min.), the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 12. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only: if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 13. operation within the t rad (max) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only: if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t caa . 14. ac measurements assume t t = 2 ns. 15. either t dzc or t deo must be satisfied. 16. either t cdd or t odd must be satisfied. 17. when using self refresh mode, the following refresh operations must be performed to ensure proper dram oper- ation: if row addresses are being refreshed on an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror ?distributed/burst; or cbr ?burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from self refresh. 18. t off is referenced from the rising edge of ras or cas , whichever occurs last.
8 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a waveforms of read cycle waveforms of early write cycle ras we i/o v a lid d a t a -out address column a ddress r o w a ddress oe 311816500-05 v a lid d a t a -in ucas , lcas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rad t rah t asc t cah t car t caa t o a c t ca c t dzc t ra c t dzo t lz t csh t rsh t cas t ar t rc t rp t crp t rch t cdd t off t ofz t rcs t rrh t ras t rcd t csh (4) t rcd (6) 311816500-06 column a ddress v a lid d a t a -in high-z ras we oe i/o address r o w a ddress ucas , lcas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t crp t ar t rah t rad t asc t cah t wch t cwl t wp t wcr t dhr t r wl t rsh t cas t car t rc t rp t crp t ras t asr t ds t dh don? care undefined
9 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a waveforms of write cycle ( oe controlled write) waveforms of read-modify-write cycle r o w a ddress r o w a ddress column a ddress 311816500-07 v a lid d a t a -in ras we oe i/o address ucas , lcas v ih v il v ih v il v ih t crp t asr t rad t rah t asc t w oh t ds t oed t crp t car t cah t cwl t r wl t wp t dh t csh t cas t rsh t rcd t ar t ras t rc t rp v il v ih v il v ih v il v ih v il column address r o w address v v 311816500-08 v a lid d a t a -out v a lid d a t a -in oh ol ras we oe i/o address ucas , lcas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t asr t rad t dzo t dzc t rah t asc t cah t a wd t cwd t r wd t cwl t r wl t wp t dh t ds t oez t oed t crp t ar t ras t rp t crp t r wc t csh t cas t rsh t ca c t o a c t caa t ra c t lz r o w a ddress don? care undefined
10 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a waveforms of edo page mode read cycle waveforms of edo page mode write cycle column address r o w address column address column address ras we oe i/o address ucas , lcas 311816500-09 t off t oez t oez t clz t coh t oez v alid d a t a out v alid d a t a out v alid d a t a out v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t rcd t pc t cp t ar t rp t crp t rhcp t rasp t rsh(r) t cas t car t cas t cas t csh t rah t rch t caa t cap t o a c t ca c t ca c t ra c t o a c t ca c t hz t lz t o a c t rch t rrh t cah t cah t rcs t rcs t cah t asr t rcs t asc t asc t caa r o w add column address v alid da t a in column address column address v alid d a t a in v alid d a t a in ras we oe i/o address open open 311816500-10 ucas , lcas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t crp t cas t csh t rah t rah t rad t cwl t cwl t cwl t wcs t wp t ds t ds t dh t dh t dh t ds t wp t wp t wch t wch t r wl t wch t wcs t wcs t cah t cah t asc t car t asc t cah t cas t cas t rsh t crp t ar t rasp t pc t cp t rp t rcd don? care undefined
11 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a waveforms of edo page mode read-modify-write cycle waveforms of ras only refresh cycle r o w add column address column address column address in in out in ras we oe i/o address out out 311816500-11 ucas , lcas v ih v il v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol t rasp t rcd t rad t rah t rcs t caa t caa t caa t cap t ca c t ca c t ca c t odd t odd t odd t oez t oez t oez t ra c t lz t lz t dh t dh t dh t ds t ds t ds t lz t wp t wp t a wd t a wd t a wd t o a c t o a c t o a c t r wd t cwl t cwl t cwl t r wl t wp t cwd t cwd t cpwd t r wd t asr t asc t asc t asc t cah t cah t cah t csh t cp t rp t pcm t cas t cas t cas t cas t crp t rsh t cap ras ucas , lcas 311816500-12 we, oe = don? care no te: address r o w addr v ih v il v ih v il v ih v il i/o high-z v oh v ol t crp t asr t rah t ras t rc t rp don? care undefined
12 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a waveforms of cas -before- ras refresh counter test cycle waveforms of cas -before- ras refresh cycle read cycle write cycle i/o address we we i/o d out d in ras oe oe 311816500-13 ucas , lcas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t csr t wrp t rcs t wcs t wch t r wl t cwl t ds t dh t o a c t lz t chz t oez t wrh t wrp t wrh t cp t rp t chr t ras t rsh t rrh t rch t cas i/o ras ucas , lcas 311816500-14 we, oe, = don? care no te: a 0 ? 9 v ih v il v ih v il v oh v ol t cp t rp t rp t rc t ras t off t rpc t csr t chr don? care undefined
13 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a waveforms of hidden refresh cycle (read) waveforms of hidden refresh cycle (write) 311816500-15 r o w add column address ras we oe i/o address v a lid d a t a ucas , lcas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t rcd t rsh(r) t rad t asr t asc t cah t chr t ras t ras t rp t rp t ar t rc t rc t crp t rah t rcs t lz t caa t ca c t ra c t oez t chz t o a c t rrh 311816500-16 r o w add column address v a lid d a t a -in ras we oe i/o address ucas , lcas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t crp t asr t wcs t wch t rah t rcd t rad t cah t asc t ar t rc t rc t rp t rp t ras t dhr t ds t dh t ras t rsh(r) t chr t crp don? care undefined
14 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a waveforms of self refresh cycle (optional) address we ras i/o oe 311816500-17 open ucas , lcas v ih v il v ih v il v ih v il v oh v ol v ih v il v ih v il t cp t rpc t csr t rp t rass t rps t rpc t chs functional description the v53c318165a is a cmos dynamic ram op- timized for high data bandwidth, low power applica- tions. it is functionally similar to a traditional dynamic ram. the v53c318165a reads and writes data by multiplexing an 20-bit address into a 10-bit row and a 10-bit column address. the row address is latched by the row address strobe ( ras ). the column address ?lows through?an internal address buffer and is latched by the column address strobe ( cas ). because access time is primarily dependent on a valid column address rather than the precise time that the cas edge occurs, the delay time from ras to cas has little effect on the access time. memory cycle a memory cycle is initiated by bringing ras low. any memory cycle, once initiated, must not be end- ed or aborted before the minimum t ras time has ex- pired. this ensures proper device operation and data integrity. a new cycle must not be initiated until the minimum precharge time t rp /t cp has elapsed. read cycle a read cycle is performed by holding the write enable ( we ) signal high during a ras / cas opera- tion. the column address must be held for a mini- mum specified by t ar . data out becomes valid only when t oac , t rac , t caa and t cac are all satisifed. as a result, the access time is dependent on the timing relationships between these parameters. for exam- ple, the access time is limited by t caa when t rac , t cac and t oac are all satisfied. write cycle a write cycle is performed by taking we and cas low during a ras operation. the column ad- dress is latched by cas . the write cycle can be we controlled or cas controlled depending on whether we or cas falls later. consequently, the input data must be valid at or before the falling edge of we or cas , whichever occurs last. in the cas - controlled write cycle, when the leading edge of we occurs prior to the cas low transition, the i/o data pins will be in the high-z state at the beginning of the write function. ending the write with ras or cas will maintain the output in the high-z state. in the we controlled write cycle, oe must be in the high state and t oed must be satisfied. don? care undefined
mosel vitelic v53c318165a 15 v53c318165a re v . 1.0 j an uar y 1998 extended data output page mode edo page operation permits all 1024 columns within a selected row of the device to be randomly accessed at a high data rate. maintaining ras low while performing successive cas cycles retains the row address internally and eliminates the need to reapply it for each cycle. the column address buffer acts as a transparent or flow-through latch while cas is high. thus, access begins from the occur- rence of a valid column address rather than from the falling edge of cas , eliminating t asc and t t from the critical timing path. cas latches the address into the column address buffer. during edo operation, read, write, read-modify-write or read-write- read cycles are possible at random addresses within a row. following the initial entry cycle into edo mode, access is t caa or t cap controlled. if the column address is valid prior to the rising edge of cas , the access time is referenced to the cas ris- ing edge and is specified by t cap . if the column ad- dress is valid after the rising cas edge, access is timed from the occurrence of a valid address and is specified by t caa . in both cases, the falling edge of cas latches the address and enables the output. edo provides a sustained data rate of 50 mhz for applications that require high bandwidth such as bit-mapped graphics or high-speed signal process- ing. the following equation can be used to calculate the maximum data rate: self refresh self refresh mode provides internal refresh con- trol signals to the dram during extended periods of inactivity. device operation in this mode provides additional power savings and design ease by elimi- nation of external refresh control signals. self re- fresh mode is initialed with a cas before ras (cbr) refresh cycle, holding both ras low (t rass ) and cas low (t chd ) for a specified period. both of these parameters are specified with minimum val- ues to guarantee entry into self refresh operation. once the device has been placed in to self refresh mode the cas clock is no longer required to main- tain self refresh operation. the self refresh mode is terminated by returning the ras clock to a high level for a specified (t rps ) minimum time. after termination of the self refresh cycle normal accesses to the device may be initiat- ed immediately, poviding that subsequest refresh cycles utilize the cas before ras (cbr) mode of operation. data output operation the v53c318165a input/output is controlled by oe , cas , we and ras . a ras low transition en- ables the transfer of data to and from the selected row address in the memory array. a ras high tran- sition disables data transfer and latches the output data if the output is enabled. after a memory cycle is initiated with a ras low transition, a cas low transition or cas low level enables the internal i/o path. a cas high transition or a cas high level dis- ables the i/o path and the output driver if it is en- abled. a cas low transition while ras is high has no effect on the i/o data path or on the output driv- ers. the output drivers, when otherwise enabled, can be disabled by holding oe high. the oe signal has no effect on any data stored in the output latch- es. a we low level can also disable the output driv- ers when cas is low. during a write cycle, if we goes low at a time in relationship to cas that would normally cause the outputs to be active, it is neces- sary to use oe to disable the output drivers prior to the we low transition to allow data in setup time (t ds ) to be satisfied. power-on after application of the v cc supply, an initial pause of 200 m s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a ras clock). eight initialization cycles are required after extended periods of bias without clocks (greater than the refresh interval). during power-on, the v cc current requirement of the v53c318165a is dependent on the input levels of ras and cas . if ras is low during power-on, the device will go into an active cycle and i cc will ex- hibit current transients. it is recommended that ras and cas track with v cc or be held at a valid v ih dur- ing power-on to avoid current surges. data rate 1024 t r c 1023 t p c + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =
16 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a table 1. v53c318165a data output operation for various cycle types cycle type i/o state read cycles data from addressed memory cell cas-controlled write cycle (early write) high-z we -controlled write cycle (late write) oe controlled. high oe = high-z i/os read-modify-write cycles data from addressed memory cell edo read cycle data from addressed memory cell edo write cycle (early write) high-z edo read-modify-write cycle data from addressed memory cell ras -only refresh high-z cas -before- ras refresh cycle high-z cas -only cycles high-z
17 v53c318165a re v . 1.0 j an uar y 1998 mosel vitelic v53c318165a package diagrams 42-pin 400 mil soj 50/44-pin 400 mil tsop-ii 1.08 ?.010 [27.41 ?.25 ] 0.05 [1.27] 1.0 [25.4] 0.017 0.004 [0.43 0.1] 0.004 [0.1] 0.045 [1.15] min 0.145 [3.68] max .406 ?.012 [10.3 ?.3 ] .441 0.006 [11.2 0.15 ] 42 1 22 21 0.370 0.010 [9.4 0.25] .406 ?.012 (1) [10.3 ?0.3] .441 ?.006 [11.2 ?.15 ] (1) 0.2 unit in inches [mm] 0.81 [.032] max +0.12 ?.05 0.008 +0.005 ?.002 0.088 0.004 [2.24 0.1] (1) does not include plastic or metal protrusion of 0.010 [0.25] max per side. 50 26 36 40 1 25 15 11 0.016 +0.002 ?.004 0.4 +0.05 ?.1 0.006 +0.003 ?.001 0.15 +0.08 ?.03 0.008 [0.2] 44x m unit in inches [mm] 0.004 0.002 [0.1 0.05] 0.031 [0.8] 0.039 0.002 [1 0.05] 0.4 0.005 [10.16 0.13] 0.463 0.008 [11.76 0.2] 0.047 max [1.2 max] 0.004 [0.1] 0.825 0.005 [20.95 0.13] does not include plastic or metal protrusion of 0.010 [0.25] max. per side 1 1 0.020 0.004 [0.5 0.1]
mosel vitelic w orld wide offices v53c318165a u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 011-852-665-4883 fax: 011-852-664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 011-886-2-545-1213 fax: 011-886-2-545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 011-886-35-783344 fax: 011-886-35-792838 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 011-81-43-299-6000 fax: 011-81-43-299-6555 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ?cop yr ight 1998, mosel vitelic inc. 1/98 pr inted in u .s .a. mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 u .s. sales offices

▲Up To Search▲

Price & Availability of V53C318165A50

	To Download V53C318165A50 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .